The unusual nominal voltage of 750 V is intended to allow additional leeway for 400 V or 500 V battery and bus applications compared to 650 V devices. Improvements over the company’s third generation mean that “Gen4 750V transistors are better than Gen3630V transistors,” UnitedSiC vp engineering Anup Bhalla told Electronics Weekly – see table below.
For example, an improved unit cell has reduced Rds (on) / area, resulting in a smaller chip. Then, to get heat out of the smaller nozzle, the heat transfer was improved by switching to an advanced sintered nozzle mount. Ron’s rise with temperature suffered slightly (see table). The integrated diode drops <1.75 V.
|Technology generation||Gen 4||Gen 3|
|Nominal part||6 mΩ, 750 V.||7 mΩ, 650 V.|
|Typical Ron at RT||6 mΩ||6.7 mΩ|
|Ron (175 ° C) / Ron (25 ° C)||2.08||1.6|
|Qrr at 400 V, 1400 A / us||462nC||840 aC|
|Etot at 400 V, 55 A, RT, HB||560 mJ||840 mJ|
|Short circuit time at RT||8ms||3ms|
|10us surge current of the body diode allowed through at RT||1.570A||773A|
|RthJC (° C / W) typ / max||0.21 / 0.27||0.15 / 0.19|
|Relative die size||0.65||1|
There are four output devices with 18 and 60 mΩ options and a TO247 package with three or four connections. “The world just won’t let go of these packages, especially the three-lead version,” said Bhalla. Mind you, “You can draw a lot of heat from them. We’re at least trying to get people on the four-lead version, which almost halves the switching losses. “- The version with four connections has a separate source connection for the gate drive circuit.
For devices of the 4th generation, the company claims “unsurpassed performance figures with reduced switch-on resistance per unit area and low internal capacitance”.
The figures for the 18mΩ R devices with three and four wires (UJ4C075018K3S and 4S, table below) are:
- With hard switching (top right), Rds (on) x Eoss is 220 mΩμJ at 25 ° C (370 mΩμJ at 125 ° C) for a low switch-on and switch-off loss
- For soft switching (right), Rds (on) x Coss (tr) is 5 mΩnF at 25 ° C (9 mΩnF at 125 ° C) for lower conduction loss and higher frequency
The cascode design (bottom left) was retained by the company, with an internal low-voltage silicon mosfet switching the source of the SiC JFET with main power.
The specially developed physically small 25V mosfet means that no special gate drive is required and that any driver intended for silicon mosfets that can provide a 0-12V circuit can be used. The gate is ± 20 V tolerant and has a 5 V threshold for immunity.
The first four devices (below) are aimed at DC-DC conversion in in-vehicle chargers, power factor correction and solar inverters.
“We will be announcing many new generation 4 appliances over the next nine months that will further improve cost, thermal efficiency and design freedom,” said Bhalla.
The four UnitedSiC Gen 4 SiC FET components are:
|UJ4C075018K3S||18 mΩ||three lead|
|UJ4C075018K4S||18 mΩ||four lead|
|UJ4C075060K3S||60 mΩ||three lead|
|UJ4C075060K4S||60 mΩ||four lead|